FIG. 1 is a cross-sectional view of a conventional metal-oxide-semiconductor (MOS) transistor. The transistor is fabricated on a substrate 100 that is formed from a single crystal of semiconducting material, most commonly silicon. A gate structure 102 includes an insulating layer 104, a gate electrode 106, a mask (or cap) layer 108, and sidewall spacers 110. The insulating layer 104 is typically formed by growing a thin film of silicon oxide on the substrate 100. The gate electrode 106 is then formed by depositing a layer of conductive material over the oxide layer. The conductive material may be metal or doped polysilicon. The mask layer 108 and sidewall spacers 110 are formed from insulating materials such as silicon-oxide and silicon-nitride.
Source and drain regions 112 (also referred to as active regions) are then formed in the substrate on opposite sides of the gate structure. The source and drain regions 112 may be formed by ion implantation in which the substrate is bombarded with high energy impurity ions that penetrate into the substrate 100. During this process, the gate structure 102 acts as a mask and prevents ions from being implanted into the portion of the substrate under the gate structure. The transistor is then connected to other circuit elements through metal conductors, typically made from aluminum, that are arranged to form contacts with the gate electrode and the active regions.
The region of the substrate 100 directly under the gate structure between the source and drain is known as the channel region and is poorly conductive in its normal state. When a voltage is applied to the gate, the electrical conductivity of the channel region is enhanced, and current may flow between the source and drain to perform a useful function such as switching or amplification.
A typical integrated circuit (IC) chip may include millions of MOS transistors fabricated on a substrate that is part of a larger single crystal known as a wafer. Dozens of chips may be fabricated on a single wafer which is then cut into individual IC chips after the fabrication process is completed. As IC chips continue to increase in density and complexity, the dimensions of the transistor features such as the source, drain and gate must be reduced in order to pack more transistors onto a single chip. One technical challenge in reducing feature size is maintaining adequate electrical connections to the gate, source and drain of each transistor. As the feature size decreases, the contact area between the metal conductors and the silicon features decreases, and thus, the contact resistance increases.
To provide a more reliable contact through a smaller surface area, certain metals may be used to form contacts because they react with silicon to form silicides which provide a highly conductive and reliable contact. A silicide contact is typically formed by depositing a thin layer of metal over silicon regions where contacts are to be formed, and then thermally treating it to cause the silicon and metal to react and form a silicide. In some instances, for example, with a drain or source, only a portion of the silicon feature should be converted to silicide so as to preserve the semiconducting property of the remaining silicon. In other instances, for example, with a gate electrode, it may be advantageous to fully silicide the silicon to provide maximum conductivity.
One prior art technique for siliciding the gate of a MOS transistor attempts to silicide the entire gate electrode through the top surface gate. In this technique, a MOS transistor having a polysilicon gate is first fabricated in a conventional manner as shown in FIG. 1. Referring to FIG. 2, portions of the active regions are then silicided through a self-aligned silicide (salicide) process to form silicide contacts 114 for the source and drain 112. Lightly doped drain (LDD) regions 116 are formed on either side of the channel region to reduce the electric field strength near the edges of the gate and its accompanying adverse effects.
An insulating layer 118 of silicon-oxide or silicon-nitride is next formed over the entire substrate 100. A portion of the insulating layer 118 is then removed through a planarization process such as chemical mechanical polishing (CMP), along with the mask layer 108 and portions of the sidewall spacers 110 to expose the gate layer 106 as shown in FIG. 2. A thin layer of metal 120 such as titanim (Ti), cobalt (Co), or nickel (Ni) is deposited over the entire wafer, as shown in FIG. 3, and then thermally treated to cause the metal to react with the polysilicon and form a silicide layer 122. Unreacted metal on the surface of the protective layer is removed through an etching process.
Although much of the gate layer is silicided through this process, it may be difficult or impossible to fully silicide the gate layer because of the small contact area between the metal layer and the polysilicon gate. To provide more complete silicidation, another prior art technique exposes both the top and sides of the gate layer to the metal layer. This technique also begins by forming a MOS transistor having a polysilicon gate in a conventional manner. The gate layer 106 and active regions are then partially silicided through a salicide process to form silicide layers 124 as shown in FIG. 4. An insulating layer 126 is then deposited over the entire substrate 100. The insulating layer 126 and sidewall spacers 110 are etched to expose not only the top surface of the gate layer, but also portions of the sidewalls as shown in FIG. 5. Another metal layer 128 is formed over the top and sidewalls of the gate layer 106 as shown in FIG. 6, and the structure is thermally treated again to fully silicide the gate layer.
Although the process shown in FIGS. 4-6 may fully silicide the entire gate, it tends to produce a gate having unacceptable properties. For example, the corners of the gate layer may be rounded off, and the sidewalls may bulge outward. This makes further processing difficult, results in irregular device geometries, and may increase the parasitic capacitance between adjacent gate structures. This process may also create voids in the gate layer 106 as the polysilicon is consumed by the silicidation process, especially at the bottom of the gate layer 106 where it meets gate oxide layer.